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TMS320DM335图片
 产品型号:TMS320DM335
 库存:2000
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 详细介绍

TMS320DM335_德州仪器推出数字媒体片上系

TMS320DM335

The DM335 processor is a low-cost, low-power processor providing advanced graphical user interface for display applications that do not require video compression and decompression. Coupled with a video processing subsystem (VPSS) that provides 720p display, the DM335 processor is powered by a 135/216-MHz ARM926EJ-S core so developers can create feature-rich graphical user interfaces allowing customers to interact with their portable, electronic devices such as video-enabled universal remote controls, Internet radio, e-books, video doorbells, and digital telescopes. The new DM335 is packed with the same peripherals as its predecessor, the TMS320DM355 device, including high-speed USB 2.0 on-the-go, external memory interface (EMIF), mobile DDR/DDR2, two SDIO ports, three UART Ports, two Audio Serial Ports, three SPI Ports, and SLC/MCL NAND Flash memory support. These peripherals help customers create DM335 processor-based designs that add video and audio excitement to a wide range of today's static user-interface applications while keeping silicon costs and power consumption low. The new digital media processor is completely scalable with the DM355 processor and Digital Video Evaluation Board (DVEVM), allowing customers to utilize their same code for their new DM335 processor focused designs.

The new DM335 device delivers a sophisticated suite of capabilities allowing for flexible image capture and display. Through its user interface technology, such as a four-level on-screen display, developers are able to create picture-within-picture and video-within-video as well as innovative graphic user interfaces. This is especially important for portable products that require the use of button or touch screen, such as portable karaoke, video surveillance and electronic gaming applications. Additional advanced capture and imaging technologies include support for CCD/CMOS image sensors, resize capability and video stabilization. The 1280-by-960-pixel digital LCD connection runs on a 75-MHz pixel clock and supports TV composite output for increased expandability. This highly integrated device is packaged in a 13 x 13 mm, 337 pin , 0.65 mm pitch BGA package.

The DM335 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates:

The DM335 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:

The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE provides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output.

The DM335 peripheral set includes:

For software development support the DM335 has a complete set of ARM development tools which include: C compilers, assembly optimizers to simplify programming and scheduling, and a Windows?debugger interface for visibility into source code execution.

产品特性
  • Highlights
    • High-Performance Digital Media System-On-Chip (DMSoC)
    • Up to 216-MHz ARM926EJ-STM Clock Rate
    • Digital HDTV (720p/1080i) output for connection to external encoder
    • Video Processing Subsystem
      • Hardware IPIPE for Real-Time Image Processing
      • Up to 14-bit CCD/CMOS Digital Interface
      • Histogram Module
      • Resize Image 1/16x to 8x
      • Hardware On-Screen Display
      • Up to 75-MHz Pixel Clock
      • Composite NTSC/PAL video encoder output
    • Peripherals include DDR and mDDR SDRAM, 2 MMC/SD/SDIO and SmartMedia Flash Card Interfaces, USB 2.0, 3 UARTs and 3 SPIs
    • Enhanced Direct-Memory-Access (EDMA)
    • Configurable Power-Saving Modes
    • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
    • 3.3-V and 1.8-V I/O, 1.3-V Core
    • Debug Interface Support
    • Up to 104 General-Purpose I/O (GPIO) Pins
    • 337-Pin Ball Grid Array at 65 nm Process Technology
  • High-Performance Digital Media System-On-Chip (DMSoC)
  • Up to 216-MHz ARM926EJ-STM Clock Rate
  • Digital HDTV (720p/1080i) output for connection to external encoder
  • Video Processing Subsystem
    • Hardware IPIPE for Real-Time Image Processing
    • Up to 14-bit CCD/CMOS Digital Interface
    • Histogram Module
    • Resize Image 1/16x to 8x
    • Hardware On-Screen Display
    • Up to 75-MHz Pixel Clock
    • Composite NTSC/PAL video encoder output
  • Hardware IPIPE for Real-Time Image Processing
  • Up to 14-bit CCD/CMOS Digital Interface
  • Histogram Module
  • Resize Image 1/16x to 8x
  • Hardware On-Screen Display
  • Up to 75-MHz Pixel Clock
  • Composite NTSC/PAL video encoder output
  • Peripherals include DDR and mDDR SDRAM, 2 MMC/SD/SDIO and SmartMedia Flash Card Interfaces, USB 2.0, 3 UARTs and 3 SPIs
  • Enhanced Direct-Memory-Access (EDMA)
  • Configurable Power-Saving Modes
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
  • 3.3-V and 1.8-V I/O, 1.3-V Core
  • Debug Interface Support
  • Up to 104 General-Purpose I/O (GPIO) Pins
  • 337-Pin Ball Grid Array at 65 nm Process Technology
  • High-Performance Digital Media System-on-Chip
    • 135-, 216-MHz ARM926EJ-S? Clock Rate
    • Fully Software-Compatible With ARM?
    • Extended Temperature 135- and 216-MHz Devices are Available
  • 135-, 216-MHz ARM926EJ-S? Clock Rate
  • Fully Software-Compatible With ARM?
  • Extended Temperature 135- and 216-MHz Devices are Available
  • ARM926EJ-S Core
    • Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM? Jazelle? Technology
    • EmbeddedICE-RT? Logic for Real-Time Debug
  • Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets
  • DSP Instruction Extensions and Single Cycle MAC
  • ARM? Jazelle? Technology
  • EmbeddedICE-RT? Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 32K-Byte RAM
    • 8K-Byte ROM
    • Little Endian
  • 16K-Byte Instruction Cache
  • 8K-Byte Data Cache
  • 32K-Byte RAM
  • 8K-Byte ROM
  • Little Endian
  • Video Processing Subsystem
    • Front End Provides:
      • Hardware IPIPE for Real-Time Image Processing
      • Up to 14-bit CCD/CMOS Digital Interface
      • 16-/8-bit Generic YcBcR-4:2 Interface (BT.601)
      • 10-/8-bit CCIR6565/BT655 Interface
      • Up to 75-MHz Pixel Clock
      • Histogram Module
      • Resize Engine
        • Resize Images From 1/16x to 8x
        • Separate Horizontal/Vertical Control
        • Two Simultaneous Output Paths
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Composite NTSC/PAL video encoder output
      • 8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Digital HDTV (720p/1080i)output for connection to external encoder
  • Front End Provides:
    • Hardware IPIPE for Real-Time Image Processing
    • Up to 14-bit CCD/CMOS Digital Interface
    • 16-/8-bit Generic YcBcR-4:2 Interface (BT.601)
    • 10-/8-bit CCIR6565/BT655 Interface
    • Up to 75-MHz Pixel Clock
    • Histogram Module
    • Resize Engine
      • Resize Images From 1/16x to 8x
      • Separate Horizontal/Vertical Control
      • Two Simultaneous Output Paths
  • Hardware IPIPE for Real-Time Image Processing
  • Up to 14-bit CCD/CMOS Digital Interface
  • 16-/8-bit Generic YcBcR-4:2 Interface (BT.601)
  • 10-/8-bit CCIR6565/BT655 Interface
  • Up to 75-MHz Pixel Clock
  • Histogram Module
  • Resize Engine
    • Resize Images From 1/16x to 8x
    • Separate Horizontal/Vertical Control
    • Two Simultaneous Output Paths
  • Resize Images From 1/16x to 8x
  • Separate Horizontal/Vertical Control
  • Two Simultaneous Output Paths
  • Back End Provides:
    • Hardware On-Screen Display (OSD)
    • Composite NTSC/PAL video encoder output
    • 8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output
    • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
    • Digital HDTV (720p/1080i)output for connection to external encoder
  • Hardware On-Screen Display (OSD)
  • Composite NTSC/PAL video encoder output
  • 8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output
  • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
  • Digital HDTV (720p/1080i)output for connection to external encoder
  • External Memory Interfaces (EMIFs)
    • DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
    • Asynchronous16-/8-bit Wide EMIF (AEMIF)
      • Flash Memory Interfaces
        • NAND (8-/16-bit Wide Data)
        • OneNAND(16-bit Wide Data)
  • DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
  • Asynchronous16-/8-bit Wide EMIF (AEMIF)
    • Flash Memory Interfaces
      • NAND (8-/16-bit Wide Data)
      • OneNAND(16-bit Wide Data)
  • Flash Memory Interfaces
    • NAND (8-/16-bit Wide Data)
    • OneNAND(16-bit Wide Data)
  • NAND (8-/16-bit Wide Data)
  • OneNAND(16-bit Wide Data)
  • Flash Card Interfaces
    • Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
    • SmartMedia
  • Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
  • SmartMedia
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • USB Port with Integrated 2.0 High-Speed PHY that Supports
    • USB 2.0 Full and High-Speed Device
    • USB 2.0 Low, Full, and High-Speed Host
  • USB 2.0 Full and High-Speed Device
  • USB 2.0 Low, Full, and High-Speed Host
  • Three 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
  • One 64-Bit Watch Dog Timer
  • Three UARTs (One fast UART with RTS and CTS Flow Control)
  • Three Serial Port Interfaces (SPI) each with two Chip-Selects
  • One Master/Slave Inter-Integrated Circuit (I2C) Bus?
  • Two Audio Serial Port (ASP)
    • I2S and TDM I2S
    • AC97 Audio Codec Interface
    • S/PDIF via Software
    • Standard Voice Codec Interface (AIC12)
    • SPI Protocol (Master Mode Only)
  • I2S and TDM I2S
  • AC97 Audio Codec Interface
  • S/PDIF via Software
  • Standard Voice Codec Interface (AIC12)
  • SPI Protocol (Master Mode Only)
  • Four Pulse Width Modulator (PWM) Outputs
  • Four RTO (Real Time Out) Outputs
  • Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
  • Configurable Power-Saving Modes
  • Crystal or External Clock Input (typically 24 MHz or 36 MHz)
  • Flexible PLL Clock Generators
  • Debug Interface Support
    • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
    • ETB? (Embedded Trace Buffer?) with4K-Bytes Trace Buffer memory
    • Device Revision ID Readable by ARM
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • ETB? (Embedded Trace Buffer?) with4K-Bytes Trace Buffer memory
  • Device Revision ID Readable by ARM
  • 337-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
  • 90nm Process Technology
  • 3.3-V and 1.8-V I/O, 1.3-V Internal
  • Community Resources
    • TI E2E Community
    • TI Embedded Processors Wiki
  • TI E2E Community
  • TI Embedded Processors Wiki
参数parametrics
参数 TMS320DM335
Applications Consumer Electronics Medical Security Video and Imaging
Operating Systems Neutrino PrOS Integrity Windows Embedded CE Linux
ARM CPU 1 ARM9
ARM MHz (Max.) 135 216
ARM MIPS (Max.) 216
Video Capability Image Enhance
TI Video Codecs JPEG MPEG4-SP
TI Audio Codecs AAC-LC G.711 MP3 WMA
On-Chip L1 Cache 32 KB (ARM9)
General Purpose Memory Async SRAM GPMC DDR2 SDRAM mDDR NAND Flash OneNAND SmartMedia/xD
DRAM LPDDR DDR2
USB 1
MMC/SD 2
UART (SCI) 3
DAC 1
PWM (Ch) 4
I2C 1
SPI 3
DMA (Ch) Yes
Video Port (Configurable) 1 Dedicated Input 1 Dedicated Output
IO Supply (V) 1.8 3.3
Trace Enabled Yes
Operating Temperature Range (C) 0 to 85
Pin/Package 337NFBGA
Rating Catalog
数据表?(1)
标题 类型 大小 (KB) 日期
TMS320DM335 Digital Media System-on-Chip (DMSoC) PDF 1159 2010年 6月 24日
勘误表?(1)
标题 类型 大小 (KB) 日期
TMS320DM335 Digital Media System-on-Chip Silicon Erata (Revs 1.1, 1.3 and 1.4) PDF 203 2010年 1月 24日
应用手册?(9)
标题 类型 大小 (KB) 日期
构建小型嵌入式Linux 内核示例 (Rev. A) PDF 1432 2013年 7月 30日
USB 2.0 板载设计及布线指南 (Rev. A) PDF 280 2013年 7月 26日
USB 2.0 Board Design and Layout Guidelines PDF 807 2015年 3月 17日
Powering the TMS320DM335 and TMS320DM355 with the TPS650061 PDF 144 2011年 10月 13日
TMS320DM355/335 Migration Guide (Silicon revision 1.1, 1.3 and 1.4) PDF 75 2011年 1月 5日
Implementing DDR2/mDDR PCB Layout on the TMS320DM335 DMSoC PDF 127 2009年 11月 11日
EDMA v2.0 to EDMA v3.0 (EDMA3) Migration Guide PDF 292 2008年 8月 21日
TMS320DM355 DSP Power Reference Design PR742 PDF 199 2008年 8月 8日
Understanding TI's PCB Routing Rule-Based DDR Timing Specification PDF 93 2008年 7月 17日
用户指南?(17)
标题 类型 大小 (KB) 日期
TMS320DM335 DMSoC Pulse-Width Modulator User's Guide PDF 105 2010年 8月 25日
TMS320DM335 DMSoC ARM Subsystem Reference Guide PDF 1243 2010年 7月 15日
TMS320DM335 DMSoC Video Processing Back-End User's Guide PDF 2570 2008年 10月 24日
TMS320DM335 DMSoC Audio Serial Port PDF 583 2008年 7月 15日
TMS320DM335 DMSoC DDR2/mDDR Memory Controller Reference Guide PDF 577 2008年 7月 15日
TMS320DM335 DMSoC Asynchronous External Memory Interface(EMIF) PDF 783 2008年 7月 15日
TMS320DM335 DMSoC Enhanced Direct Memory Access (EDMA) Controller User's Guide PDF 1351 2008年 7月 15日
TMS320DM335 DMSoC Universal Serial Bus (USB) User's Guide PDF 1075 2008年 7月 15日
TMS320DM335 DMSoC General-Purpose Input/Output (GPIO) User's Guide PDF 362 2008年 7月 15日
TMS320DM335 DMSoC Real Time Out (RTO) User's Guide PDF 121 2008年 7月 15日
TMS320DM335 DMSoC MMC/SD Reference Guide PDF 514 2008年 7月 15日
TMS320DM335 DMSoC Peripheral Overview Reference Guide PDF 144 2008年 7月 15日
TMS320DM335 DMSoC Inter-Integrated Circuit (I2C) PDF 396 2008年 7月 15日
TMS320DM335 DMSoC Universal Asynchronous Receiver/Transmitter (UART) PDF 321 2008年 7月 15日
TMS320DM335 DMSoC Serial Peripheral Interface (SPI) PDF 328 2008年 7月 15日
TMS320DM335 DMSoC Timer/Watchdog Timer User's Guide PDF 319 2008年 7月 15日
TMS320DM335 DMSoC Video Processing Front-End User's Guide PDF 2263 2008年 7月 15日
白皮书?(3)
标题 类型 大小 (KB) 日期
“Get smart” with TI’s embedded analytics technology PDF 2059 2012年 5月 30日
Exploring Video Compression Challenges PDF 150 2009年 8月 28日
An Overview of TI's Digital Video Software Development Kit PDF 207 2009年 8月 28日
更多文献资料?(6)
标题 类型 大小 (KB) 日期
达芬奇技术概述手册 (Rev. B) PDF 2571 2008年 8月 12日
TMS320DM3x DaVinci Video Processors PDF 117 2010年 4月 11日
TMS320DM3x Highlights PDF 140 2009年 3月 3日
Complimentary Analog Devices for the DM335 Digital Media Processor PDF 158 2009年 2月 17日
TMS320DM335 Technical overview [MP4] MP4 82272 2009年 1月 31日
TMS320DM335 Digital Media Processor Overview [MP4] MP4 52559 2009年 1月 31日
设计套件与评估板?(1)
培训内容 型号 类型
TMS320DM355 数字视频评估模块 TMDSEVM355 开发套件
 
描述 器件型号 公司 工具类型
用 TPS650061 给 TMS320DM335 和 TMS320DM355 供电 PR2047 Texas Instruments 参考设计
SEED-DVS357   Beijing Arrow SEED Technology Co.,Ltd. 参考设计
软件?(2)
培训内容 型号 类型
SYS/BIOS 实时内核 SYSBIOS DSP/BIOS 实时内核
多媒体框架产品 (MFP) - 编解码器引擎,框架组件和 xDAIS TMDMFP 应用软件与框架
开发工具?(2)
培训内容 型号 类型
XDS560 高性能调试探针 XDS560 JTAG 仿真器/分析器
Code Composer Studio (CCS) 集成开发环境 (IDE) CCSTUDIO 软件开发工具、IDE、编译器
模型?(2)
标题 种类 类型 大小 (KB) 日期
DM335 ZCE BSDL Model BSDL Model ZIP 8?KB 2008年 7月 15日
订购型号Ordering
型号 状态 温度 (oC) 价格(美元) | Quantity 封装 | 引脚 器件标记 封装数量 | 载体
TMS320DM335CZCE216 NRND   24.05 | 1ku NFBGA?(ZCE) | 337 DM335CZCE 216 TMS320 DM355ZCE 216 160
TMS320DM335DZCE135 ACTIVE 0 to 85 9.05 | 1ku NFBGA?(ZCE) | 337 DM335DZCE 135 TMS320  
TMS320DM335DZCE216 ACTIVE 0 to 85 10.25 | 1ku NFBGA?(ZCE) | 337 DM335DZCE 216 TMS320 160
TMS320DM335ZCEA135 OBSOLETE -40 to 100 联系客服 NFBGA?(ZCE) | 337 DM335ZCE A135 TMS320 DM335ZCE A135  
TMS320DM335ZCEA216 OBSOLETE -40 to 100 联系客服 NFBGA?(ZCE) | 337 DM335ZCE A216 TMS320 DM335ZCE A216  

这里所列出的美国报价单仅供预算参考,指美元报价(规定订量的每片美元,美国离岸价),如有修改不再另行通知。由于地区关税、商业税、汇率及手续费原因,国际报价可能不同。对于特殊批量报价,请与君硅科技 联络。对于评估板和套件的报价是指一个单位价格。



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